As integrated circuit devices typically are built up on a substrate from successively applied and patterned layers, it generally is desirable to planarize underlying layers in order to obtain a satisfactory margin for photolithography for subsequently applied layers. Conventional planarization techniques include reflow techniques, etch-back techniques and chemical-mechanical polishing (CMP) techniques, i.e., combined etching and abrasive polishing techniques which typically use an abrasive etching slurry in conjunction with a polishing pad to remove material from a substrate surface. As is well-known to those skilled in the art, CMP may be particularly advantageous because it can achieve planarization at lower temperatures than etching or reflow techniques.
When utilizing CMP, it generally is important to minimize initial global step difference, i.e., spatial variation in the initial height of the material to be polished, in order to reduce pad deformation and improve the planarization achieved. As illustrated in FIGS. 1A-1C, wide and narrow trenches 3,4 may be formed in a substrate 10 by forming a silicon dioxide layer 12 and an etching protection layer 14 on the substrate 10, patterning the layers to form patterns 15, and using the patterns 15 as an etching mask to produce the wide and narrow trenches C,D. To form wide and narrow isolation regions 17,18, an insulating material layer 16 may be formed on the substrate 10 to fill the trenches C,D. The insulating material layer 16 may then be planarized to form the isolation regions 17,18.
Because of the step difference E generated in the insulating material layer 16 due to the wide trench 3, however, the wide isolation region 17 may deviate from planarity, a phenomenon referred to as "dishing." Moreover, because the trenches formed for a typical integrated circuit generally are nonuniformly distributed, a nonuniform distribution of the insulating material layer generally occurs across the surface of the substrate, which may increase global step difference and reduce the margin for CMP.